High-speed data communication systems frequently rely on dock and data recovery (CDR) circuits within the receiver rather than transmitting a reference clock with the data. For example, serial data communication may include the use of a serializer-deserializer (SERDES) at each end of a communication link. Within a SERDES, a CDR may extract a clock that is embedded in the incoming data stream, Once a dock is recovered, the clock is used to sample the incoming data stream to recover individual bits.
A CDR can make use of a fractional-N phase locked loop (PLL) for generating clock signals. The fractional-N PLL includes a divider for dividing the output clock and comparing the divided output dock to a reference clock. A fractional-N PLL can include a delta-sigma modulator (DSM) having a multi-stage noise shaping (MASH) circuit for generating a dithered divider signal. The fractional-N PLL uses a frequency divider to provide the integer part of the divider and the DSM to provide a fractional part of the divider, Conventional MASH 1-1 and 1-1-1 architectures can only handle fractional input ranged from 0 to 1-LSB (where LSB is the value represented by the least significant bit of the input). For example, a fractional-N PLL can implement a divider of 50.01 using an integer divider of 50 and a fractional divider of 0.01. If the divider is changed to 49.99, the integer divider can be changed from 50 to 49 without complication. However, the DSM output must travel from 0.01 to 0.99 (almost the full range), which increases the time needed to change the divider from 50 to 49.99 despite the change being only one LSB. Accordingly, there is a need for a more flexible DSM architecture that can handle expanded input ranges centered around an integer.